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iPhone 16 A18 processor isn't a 'binned' A18 Pro

Apple's branding for the A18 and A18 Pro chips.

New microphotography of the A18 and A18 Pro chips reveal the inner workings of the iPhone 16 line's chips, as well as confirming Apple isn't using chip binning right now.

Apple's chips in its products are impressive, giving other processor makers a run for their money over the years. As the designs improved, so did the performance and capabilities of its hardware, as is evident in the iPhone 16.

Following after teardowns, the next logical step is to closely examine the chips, and Chipwise has done just that. It has published photographs of the dies used in the A18 and A18 Pro.

The packaging of the chip has been consistent over the years, with TSMC using an Integrated Fan-Out Package-on-Package (InFO-PoP) method for a while. The technique stacks a DRAM package on top of the SoC die, with high-density redistribution layers and a Through InFO Via assisting to create a compact overall chip size.

In other words, Apple stacks the memory on top of the CPU and GPU, instead of having them in a separate die.

Two detailed, side-by-side microchip layouts with intricate patterns and grids labeled 'CHIPWISE Semiconductor Insights' at the bottom. Die shots of the A18 (left) and the A18 Pro (right0 [via Chipwise]

The shots of the A18 SoC shows off its 3-nanometer manufacturing process, and a fairly straightforward layout. Cores and other elements are clustered together, almost like fields in an overhead shot of a countryside landscape.

Checking over the die shot for the A18 Pro, it does at first glance appear to be very similar to the A18's version. You can see where clusters are placed in similar locations, and it would be quite easy to mistake one for the other from these images alone.

However, a more careful examination shows that Apple has included a lot more transistors on the A18 Pro. Many of the lighter sections take up a lot more space on the die compared to what's on the A18.

The images at least prove that Apple isn't simply performing chip binning. This is a process where a Pro chip would be made, but faulty versions with a failed core could be repackaged as non-Pro A18 chips instead.

It was believed that the A18 was going to be a binned version of the A18 Pro, since it relies on one fewer GPU core. With similar features like Apple Intelligence support and hardware-based ray tracing, it was easy to believe chip binning was at play.

With the differences evident in the shots, it seems that Apple is legitimately designing and producing two different chips, instead of relying on chip binning.



11 Comments

netrox 1510 comments · 12 Years

Are there other processors with DRAM embedded inside chips? I don't recall any. That definitely interests me, because if that's the case, I imagine the Mac Studio Ultra with M4 or M5 having RAM embedded will be knocking our socks off with massive memory bandwidth and performance (reduced latency as well).

ljbyrne 20 comments · 14 Years

Just noting, this is not new for Apple. They have embedded DRAM inside their chips for a while, including all the M series chips.

tht 5654 comments · 23 Years

netrox said:
Are there other processors with DRAM embedded inside chips? I don't recall any. That definitely interests me, because if that's the case, I imagine the Mac Studio Ultra with M4 or M5 having RAM embedded will be knocking our socks off with massive memory bandwidth and performance (reduced latency as well).

The DRAM isn’t embedded “inside chips”. It’s a package on package (POP), where the DRAM package is layered on top of the chip package. The DRAM interface is the standard LPDDR5 (presumably) interface, pins and all. No bandwidth advantage per pin or per DRAM package. 


Once more, look at the DRAM packages on an M2, M3, M4 package. There, it is adjacent or on the side of the chip package. In the A-series SoCs, one package is just layered on top of chip package. Saves floor area. Same pin layouts. Probably saves a little bit of power. Just a little. 

Apple is quoting higher bandwidth on A18 series SoCs likely due to faster DRAM, like 6800 to 8400  Mbit/s per pin data rates. 

The M Pro, Max and Ultra SoC use standard LPDDR chips, but have 4, 6, 8, 12, 16 memory channels to achieve their bandwidths. 

tht 5654 comments · 23 Years

These die shots do not look like they are at the same scale? The A18 Pro chip looks physically bigger, with larger SLC and L2 caches, plus the stated 6th GPU core. The Neural engine is in the middle? But it looks bigger than it typically does.

The CPU complex looks odd? They are bilaterally symmetric, but are not typically rectangular. Have to wait for a floorplan.

beowulfschmidt 2361 comments · 12 Years

To be fair, there's nothing inherently wrong with chip binning.  It allows the manufacturer to use "imperfect" chips for other purposes, mitigating some wastage.