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Intel touts Core microarchitecture, lower-power chips in opening keynote

Under pressure from smaller rival AMD, Intel Corp. at its twice annual developers conference on Tuesday offered new details of its forthcoming Intel Core microarchitecture, which will form the foundation for its next-generation, multi-core server, desktop and mobile processors due later this year.

The first Intel Core microarchitecture products built on the chip maker\'s advanced 65nm process technology will deliver both higher-performing and more energy-efficient processors that the company says will spur more stylish, quieter and smaller computers.

The chips, which will use less power than Intel\'s current lineup and have multiple cores to process data faster, should begin finding their way into notebooks, desktops and servers in the third quarter of the year. By using less power, server chips based on the new Core microarchitecture will reduce electricity and real-estate associated costs, the company said.

Justin Rattner, Intel Senior Fellow and chief technology officer, explained that the Intel Core microarchitecture is the foundation for delivering greater energy-efficient performance first seen in the Intel Core Duo processor earlier this year.

The architecture builds on the power-saving philosophy that begun with the Mobile Intel Pentium-M processor microarchitecture and greatly expands it, incorporating many new innovations as well as existing Intel Pentium 4 processor technologies such as wide data pathways and streaming instructions.

Some of the new advances of the architecture include Wide Dynamic Execution, a feature that delivers more instructions per clock cycle, improving execution and energy efficiency, and Intelligent Power Capability, which helps reduce overall power consumption by intelligently powering on individual logic subsystems only when required.

The Core microarchitecture also includes a shared L2 cache, dubbed Advanced Smart Cache, which reduces power by minimizing memory traffic and increasing performance by allowing one core to utilize the entire cache when the other core is idle. Other features include Smart Memory Access for hiding memory latency and hence increasing performance, as well as Advanced Digital Media Boost, which doubles the execution speed of all 128-bit SSE, SSE2 and SSE3 instructions.

\"The Intel Core microarchitecture is a milestone in enabling scalable performance and energy efficiency,\" said Rattner. \"Later this year it will fuel new dual-core processors and quad-core processors in 2007 that we expect to deliver industry leading performance and capabilities per watt. People will see systems that can be faster, smaller and quieter with longer battery life and lower electric bills.\"

In his keynote, Rattner showed how the company\'s forthcoming \"Conroe\" desktop processor could provide roughly a 40 percent boost in performance and a 40 percent decrease in power as compared to the current Pentium D 950 processor. Meanwhile, \"Merom,\" the successor to the \"Yonah\" Core Duo processor, will provide about a 20 percent speed increase without drawing any additional power.

Most importantly for Intel, Rattner, who acknowledging that Intel is under \"tremendous competitive pressure\" from AMD, announced that its forthcoming \"Woodcrest\" server chip will deliver an 80-percent gain in performance alongside a 35 percent reduction in power consumption.

Rattner\'s opening keynote presentation is to be followed by presentations from several other Intel execs. Coverage will follow.