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TSMC will use updated 'N7 Pro' 7-nanometer process for 'A13' chip manufacturing

Apple's "A13" processor will use a 7-nanometer process for its production, but chip foundry TSMC is reportedly planning to use a different enhanced process to the current version it has come up with, named "N7 Pro."

TSMC's use of a 7-nanometer process for the next generation of Apple system-on-chips is not unexpected, with TSMC widely believed to not only continue to be the only supplier of A-series chips in 2019, but also keeping to the same process level. According to one report, TSMC will be making some changes to the process.

The Chinese Commercial Times claims TSMC will move to a 7-nanometer extreme ultraviolet lithography (EUV) process that has the potential for more accurate chip production and more intricate designs, named "N7+." HiSilicon's Kirin 985 chips will be the first to use N7+ in its production, but the Apple-designed "A13" will be the next to go into manufacturing at the firm.

For the A-series chip, TSMC will be bringing out an alternate form of its N7+ process which it calls "N7 Pro." It is unclear exactly what the difference is between N7 Pro and N7+, but it will reportedly be ready for volume production late in the second quarter, in time for A-series production for the fall iPhone refresh.

TSMC has come up with a 5-nanometer design infrastructure that could be used to design future A-series chips and other processors. Current speculation has the "A14" using a 5-nanometer production process for the 2020 iPhones.



14 Comments

iOS_Guy80 905 comments · 5 Years

What happens after the 0-nanometer design infrastructure?

radarthekat 3904 comments · 12 Years

iOS_Guy80 said:
What happens after the 0-nanometer design infrastructure?

What happens at 3nm?  Things should get interesting in a couple years. 

https://semiengineering.com/big-trouble-at-3nm/

tnet-primary 242 comments · 13 Years

What does this get us?  Better battery life?

wood1208 2938 comments · 10 Years

Like Intel's 14nm-> 14nm+ ->14nm++. Tweaking node and squeeze every bit of performance out of it. TSMC, next 5nm in 2020 or 2021 ? But, like Intel's upcoming Lakefield approach, attention will move to 3D packing to integrate more on SOC than just keep reducing node size. Physics have it's limits.

GeorgeBMac 11421 comments · 8 Years

iOS_Guy80 said:
What happens after the 0-nanometer design infrastructure?

If the math holds,  as you approach zero:  infinity -- Or, in this case, infinite power.
... "One chip to rule them all"