TSMC preps for 2nm chip production trial for iPhone 17

Apple's chip partner is about to start trial production of chips using a 2-nanometer fabrication process, ahead of making the A19 chip destined for the iPhone 17.

Since 2022, TSMC has been planning to mass produce chips using a 2-nanometer process by 2025. The schedule would effectively make the A19 chip inside the iPhone 17 Pro the first of its kind to use the process.

Apple's famously long production schedules for its extremely complex supply chain means that companies making components need to work early to get their processes in line. In a Tuesday report, it seems TSMC is doing just that.

According to Liberty Times via ET News, TSMC will commence trial production of 2-nanometer semiconductors in its Baoshan plant starting in the next week. Equipment was installed in the North Taiwan plant in the second quarter of 2023.

The trial production for the third quarter will be earlier than anticipated, with the market expecting TSMC's trial to happen in the fourth quarter. It is now thought that the accelerated schedule is to help TSMC reach a stable yield before actually starting mass production.

Shifting to a 2-nanometer process should also include a switch to gate all around (GAA) technology, as well as back-side power supply (BSPR) technology. It is expected that the new tech should improve performance and power efficiency in chips that use the technique, which in turn will help boost the A19's performance.

Apple is extremely keen to start producing 2-nanometer chips with TSMC. In May, COO Jeff Williams paid a visit to Taiwan to discuss 2-nanometer production, as well as the development of more AI-forward chips to help further the cause of Apple Intelligence.

6 Comments

harrykatsaros 8 Years · 91 comments

About 5 months ago

Is sub 1nm possible or are we reaching the limits of semiconductor miniaturisation? What is the physical limit?

blastdoor 15 Years · 3594 comments

About 5 months ago

harrykatsaros said:

Is sub 1nm possible or are we reaching the limits of semiconductor miniaturisation? What is the physical limit?

That's the evergreen question for these types of stories. I'll give a variation on the standard answer.

These process names no longer have very much connection to physical reality -- they are just marketing labels. To achieve improvements in performance, power, and area (PPA -- the chip manufacturer's holy trinity), companies used to be able to just use shorter wavelengths of ultraviolet light to burn circuit designs onto silicon. That approach has not entirely run out of gas, but the red light is definitely flashing on the dashboard. So for many years now, companies like TSMC and Intel have been turning to other strategies to improve PPA without necessarily reducing the feature size of those circuits and transistors.

At best, you can think of the marketing labels as something like "if we only increased PPA using the old approach of reducing the wavelength of light, what would the smallest feature size be?" and then they use that as the label. But I'm not sure they even do that. All you can really say is that when then increment the number, they are trying to communicate that they've made a noticeable improvement in PPA. When they don't increment the number, but throw some letters or other symbols after it, they're indicating that they've made some small progress or tweak for a specific class of product, but it's not anything to get super excited about.

So that's a long way of saying -- your question is kind of irrelevant because those numbers don't mean what you think they mean.

blastdoor 15 Years · 3594 comments

About 5 months ago

When the timing of N2 was first being reported, I thought it was fanciful to imagine that Apple would be including N2-based chips in their 2025 product lineup.

But these stories are now starting to make me think it will happen after all. It sounds like Apple+TSMC are making a full court press on this process. I wonder if that's partly due to Intel's 18A process coming out next year...