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Apple's Cook awarded $58M worth of AAPL stock for meeting performance goals, sells none

Apple CEO Tim Cook on Monday acquired 560,000 vested restricted stock units, split evenly between time- and performance-based awards, worth nearly $58 million, according to a U.S. Securities and Exchange Commission filing.




As noted in the SEC document, Cook chose not to sell any vested RSUs, though 290,836 shares were automatically withheld by Apple to comply with minimum statutory tax withholding requirements. Given Monday's closing price of $103.12, the remaining shares are worth roughly $29 million. In total, Cook has accumulated more than 1.17 million owned Apple shares which, if sold today, would be worth almost $121.4 million.

To receive a fully vested award, Cook had to satisfy performance metrics related to Apple's total shareholder return relative to other firms listed in the S&P 500 during a two-year period between Aug. 25, 2013 and Aug. 24, 2015, the beginning value of which calculated by averaging AAPL's closing price for 20 trading days prior to the 2013 start date. Adjusted for dividends and a 7-to-1 stock split in 2014, starting value was calculated at $68.56 per share. The ending value, set at $121.18 and adjusted for dividends, was subsequently calculated by averaging AAPL closing prices for the 20 days leading up to Aug. 24, 2015.

Contractual stipulations specified Cook's RSU award would vest in full if TSR performance fell within the top third of companies that remained in the S&P 500 over the observed two-year period. According to the filing, Apple's TSR performance of 76.76 percent ranked 46th of 458 companies, putting it in the 90th percentile. If Apple ended up in the middle or bottom third, the award would have been reduced to 50 percent or zero, respectively.

As per Cook's original compensation plan, there are 4,760,000 outstanding RSUs scheduled to vest in 700,000-unit batches on Aug. 24 in 2016 and 2021. Two 1.68 million-unit chunks will vest in six annual installments starting on Aug. 24, 2016, one of which being contingent on TSR performance.